1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly to a ultra-high current drive MOS transistor suitable for use under a low supply voltage.
2. Description of the Prior Art
In the field of the MOS transistors, with the advance of the integration technique of the MOSFETs in particular, the device having a gate length within a range equal to or less than 0.5 .mu.m has been studied and developed at various places. In 1974, R. L. Dennard et al. have proposed the so-called scaling method for the MOSFET down-scaling. This method indicates that when the size of one composing element (e.g., channel length) of an element is required to be reduced, the operating characteristics of the transistor can be secured, as far as the other composing elements are reduced at the same reduction ratio. Basically, from the 1979s to the early 1990s, the higher integration technique of the MOSFETs has been realized on the basis of this scaling method.
With the advance of the higher and higher integration, however, various composing elements approach the respective limit values referred to as "limit values" so that it has become difficult to further reduce the various composing elements beyond these limit values. For instance, since the limit of the thickness of the gate insulating film is generally considered as about 3 to 4 nm, when the film thickness is reduced below this value, direct tunneling current between the gate electrode and the source/drain electrode increases, so that it has been well known that the transistor cannot operate normally.
To overcome this problem, in 1993, Fiegna et al. have proposed such a technique that although the gate insulating film thickness is fixed to about 3 nm, the composing elements other than the gate insulating film can be reduced [as reported by Document (Writer): C. Fiegna, H. Iwai, T. Wada, T. Saito, E. Sangiorgio, and B. Ricco; (Title) A new scaling methodology for the 0.1 to 0.025 .mu.m MOSFET, 'Dig. of Tech. Papers, VLSI Symp; (Source) Technol., Kyoto, pp 33-34, 1993]. On the basis of this technique, in the same year, Ono et al. have realized a transistor having a gate length of 0.04 .mu.m, [as reported by Document (Writer): M. Ono, M. Saito, T. Yoshitomi, C. Fiegna, and H. Iwai; (Title) Sub-50 nm gate length n-MOSFETs with 10 nm phosphorus source and drain junction: (Source) IEDM Tech. Dig., pp. 119 to 122, 1993].
The transistor having a gate insulating film thickness of 3 nm and a gate length of 0.04 nm was manufactured as follows: First, an isolation region had been formed on a p-type silicon substrate in accordance with LOCOS (Local Oxidation of Silicon), p-type impurities (e.g., B (boron)) were introduced into the channel forming region to such an extent that any required threshold voltage was obtained.
After that, as the gate oxide film, an oxide film of about 3 nm was formed on the surface of the silicon substrate by oxidization at 800.degree. C. for 10 min within a dry O.sub.2 atmosphere, for instance. Further, after poly silicon containing P (phosphorus) was deposited to a thickness of about 100 nm, a resist was applied, and the applied resist was patterned to obtain a gate electrode of a desired length. Further, n-type impurities were introduced into the source/drain forming region, by solid phase phosphorus diffusion from a PSG film (a silicon oxide film containing P (phosphorus)) remaining on the gate electrode side wall portion. After that, in order to improve the connection to the metal wiring portion and further to reduce the resistance of the diffusion layer portion (which exerts no influence upon the short channel effect of the transistor), n-type impurities (a dose: 5.times.10.sup.15 cm.sup.-2) were introduced in accordance with the ion implantation method, for instance. At this time, the substrate was annealed at 1000.degree. C. for 10 min, for instance for impurity diffusion and activation. After that, contact portions were opened, and metallization was formed.
In the transistor manufacture as described above, the sheet resistance (.rho.s) of the source/drain diffusion layer under the gate side wall portion was 6.2 k.OMEGA./.quadrature., and the diffusion length (i.e., the depth of the source/drain region) was 10 nm, as a result of SIMS analysis.
In the above-mentioned prior art transistor, however, since the parasitic resistance increased relatively large due to the shallow source/drain region, it was impossible to obtain a high current drive capability corresponding to the reduction of the gate length.